The process flow for fabrication of integrated semiconductor circuits may include front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MEOL process may include gate contact formation. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MEOL processes. Successful fabrication and qualification of modern semiconductor chip products requires consideration of interplay between the materials and the processes employed.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this Discussion of the Background section constitute prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.